1. Field of the Invention
The present invention relates to a technique for resolving a pixel deficiency of a liquid crystal display (LCD) device and, more particularly, to a technique for improving a pixel deficiency of a liquid crystal display device of a storage-on-common type.
2. Description of the Background Art
In general, a liquid crystal display device includes a thin film transistor TFT array substrate and a color filter substrate. The TFT array substrate includes a plurality of gate lines arranged in parallel in a line direction, a plurality of data lines arranged in a column direction and intersecting the gate lines, and TFTs formed at the intersection of the gate lines and the data lines. The color filter substrate has a plurality of color filters corresponding to unit pixels of the TFT array substrate. Liquid crystal is filled between the TFT array substrate and the color filter substrate.
The structure and operation of the TFT array substrate will now be described with reference to FIG. 1.
A TFT array substrate 100 is constructed with a plurality of gate lines 4 formed in a column direction on a substrate; a plurality of data lines 2 arranged in a line direction and intersecting the gate lines 4; a plurality of thin film transistors (T) each formed at the intersection of the corresponding gate line 4 and the corresponding data line 2; a plurality of pixel electrodes 14 each formed at a unit pixel region defined by the intersection of the corresponding gate line 4 and the corresponding data line 2; and a storage capacitor (not shown) for maintaining a signal applied from the data line for a predetermined time period.
A method of forming the storage capacitor in the liquid crystal display device generally involves forming a storage capacitor of a storage-on-gate type or forming a storage capacitor of a storage-on-common type.
The storage-on-gate structure involves a storage capacitor formed at a certain region of the gate line, while the storage-on-common structure involves a storage line formed in a liquid crystal cell and a storage capacitor formed at a certain region of the storage line.
The liquid crystal display device with the storage-on-common structure will now be described in detail with reference to the accompanying drawings.
FIG. 2 is a view showing a plane structure of a TFT array substrate of the liquid crystal display device with the storage-on-common structure.
With reference to FIG. 2, the gate lines 4 are arranged isolated in a vertical direction on the substrate, and the data lines 2 are arranged isolated in a horizontal direction. Accordingly, the gate lines 4 and the data lines 2 are arranged in a matrix form. A pixel region is defined by the intersection of the corresponding data line 2 and the corresponding gate line 4, and has a thin film transistor TFT and the pixel electrode 14. Storage lines 3 are provided between the gate lines 4 with a certain space therebetween and arranged in parallel to the gate lines 4.
Each thin film transistor TFT includes: a gate electrode 10 formed to protrude from a certain position of the gate line 4, a source electrode 8 extended from a certain position of the data line 2 and overlapping with the gate electrode 10 at its certain region, and a drain electrode 12 formed at a position corresponding to the source electrode 8 on the basis of the gate electrode 10. Accordingly, each TFT is formed at the intersection of the corresponding gate line 4 and the corresponding data line 2.
The pixel electrode 14 is formed at a portion of the pixel region of the liquid crystal cell where the TFT is not formed, and electrically contacts the drain electrode 12 through a drain contact hole 16 formed on the drain electrode 12 of the thin film transistor.
Accordingly, for each pixel region, the pixel electrode 14 and the corresponding storage line 3 overlap with each other with an insulation film (not shown) therebetween at the region where the storage line 3 of the liquid crystal cell is formed. This overlapping structure serves as a storage capacitor 18.
FIG. 3 is a sectional view taken along line I-I′ of FIG. 2. A sectional structure of the TFT will now be described in detail with reference to FIG. 3.
The gate electrode 10 is formed on the substrate 1, and a gate insulation film 30 is formed over the entire surface of the substrate 1 including the gate electrode 10. The gate electrode 10 is formed to protrude in one direction from a certain position of the gate line 4.
An active layer 36 is formed such that a semiconductor layer 32 made of amorphous silicon is formed at an upper portion of the gate insulation film 30 and an ohmic contact layer 34 made of amorphous silicon doped with high density phosphor is deposited thereon.
The source electrode 8 and the drain electrode 12 are formed as isolated with a certain space therebetween and at the upper portion of the active layer 36, facing each other.
The ohmic contact layer 34 formed at the upper portion of the semiconductor layer 32 at the region where the source electrode 8 and the drain electrode 12 are isolated is removed in the process of forming the source electrode 8 and the drain electrode 12. The semiconductor layer 32 exposed as the ohmic contact layer 34 is removed becomes a channel region of the thin film transistor.
A passivation layer 38 is formed at the entire surface of the substrate 1 exposed with the source electrode 8 and the drain electrode 12. The passivation layer 38 can be an inorganic insulation film such as SiNx or SiOx, or an organic insulation film such as benzocyclobutene (BCB), a spin-on-glass or acryl with a low dielectric constant in order to improve an aperture ratio of the liquid crystal display device.
The contact hole 16 is formed through the passivation layer 38 to expose a portion of the drain electrode 12. The pixel electrode 14 is formed at an upper portion of the passivation layer 38, and the pixel electrode 14 and the drain electrode 12 electrically contact with each other through the contact hole 16.
FIG. 4 is a sectional view taken along line II-II′ of FIG. 2. A sectional structure of the storage capacitor will now be described in detail with reference to FIG. 4.
The storage line 3 is formed on the substrate 1, and the gate insulation film 30 is formed at the entire surface of the substrate 1 including the storage line 3. The storage line 3 is formed isolated from and parallel to the gate line 4 when the gate line 4 is formed. The passivation layer 38 is formed at an upper portion of the gate insulation film 30. The passivation layer 38 is the same layer as the passivation layer 38 of the switching device of FIG. 3. The pixel electrode 14 is formed at an upper portion of the passivation layer 38, overlapping with the storage line 3 at a certain region.
In the case of the storage capacitor as shown in FIGS. 2 and 4, the storage line 3 and the pixel electrode 14 overlap each other with the gate insulation film 30 and the passivation layer 38 therebetween.
A gate drive applies a signal to every gate line, and the channel of the TFT is turned on by the applied gate signal. While the channel of the TFT is turned on, a data signal is applied to the TFT, applying a current to the pixel electrode, according to which an electric field is formed both by the pixel electrode and the common electrode, thereby driving the liquid crystal. The voltage applied to the pixel electrode through the data line forms the storage capacitor together with the storage line positioned at a lower side of the pixel electrode.
The storage capacitor serves to maintain a signal while no signal is applied to the pixel electrode. However, during the fabrication process of the unit pixel, the unit pixel can be defective due to a particle or the like generated during the fabrication, thereby failing to perform a normal driving.